When time stamping an asynchronous signal by reading a continuously clocked counter, it is desirable to first synchronise the signal to the counter clock. This ensures that the counter can be read synchronously so that a standard binary counter can be used rather than a gray code counter. Similarly when gating a counter with an asynchronous input it is desirable to first synchronise the gate signal to the counter clock. When combined with sufficient clock of gate signal jitter this ensures that averaging the count produces an unbiased estimate of the gate duration.
The above circuit depicts a conventional synchroniser. The synchroniser output SAMPLE_COUNT is used to synchronously sample the count of a synchronous counter. The time stamp resolution is one period of the counter (and synchroniser) clock. Higher resolution can be achieved by using a TDC to measure the propagation delay of the synchroniser for each input signal transition to be timestamped. The TDC measures the time interval between the leading edges of the START and STOP outputs of the synchroniser. To minimise the probability of metastability at the synchroniser output flipflops with very fast regeneration time constants should be used and the time delay before sampling the synchroniser input flipflop should be as long as possible.
When using a TDC to measure the input to output delay of a conventional synchroniser the TDC needs an input range of several clock periods. If one uses a TDC that has an input range of 1 clock cycle (e.g. a TDC taking I and Q samples of a reference sine wave at the input signal transition) then a more complex synchroniser is required.
The above circuit is for a dual phase synchroniser, signal QCLK is in quadrature with CLK. D103 and D104, the input flipflops of a pair of synchronisers, are clocked by opposite phases of CLK. D102 samples the state of QCLK at the input signal transition to be time stamped. The output of D102 is then used to select the synchroniser output for which the corresponding input flipflop can be guaranteed to meet its setup and hold timing constraints. D105 and D106 are used to increase the available settling time for D102. When using a pair of ADCs to simultaneously sample 2 reference sinwaves I and Q in phase quadrature (CLK is derived by generating a logic level signal from the I sinewave reference signal). The time stamp for the selected input signal transition can then be calculated from the sampled count and the measured phase at the input signal transition, determined from the ADC samples, as:
T*((Sampled count) - N)) + (Sampled phase)/(2π))
T is the clock period
N = 4
The START and STOP outputs are only required when using a conventional TAC or TDC.
When using I + Q sampling of a reference sinewave, the delays and timing jitter of the synchroniser aren't too critical. Thus the synchroniser logic can be implemented in an FPGA. The positive slope zero crossing of the I sine wave reference are used as the time reference. The ADC sample triggering logic must not be implemented in an FPGA as the active edge of the ADC sample control signale requires very low jitter to avoid degrading the system noise.
The above circuit is an alternative implementation of a dual phase synchroniser where the CLK is delayed by 1/4 of a clock period to generate the QCLK signal. Similarly the PPS input to the upper synchroniser is delayed by 1/2 the clock period. This eliminates the requirement to clock the input stage of the upper synchroniser with the complement of CLK. This can be useful when using an IC that has a limited number of clock pins available. In particular the synchroniser could use a 74XX374 or similar device with a single clock for D102-D109 and a 74XX74 for D101 and D102. The delays DL101 and DL102 aren't too critical unless the CLK frequency is close to the maximum specified clock frequency for the flipflops.
The extra D flipflop (D107) in the lower synchroniser ensures that the same formula can be used to extend the resolution when using an I + Q sinewave interpolator irrespective of whether the output of D105 or the output of D107 is selected to sample the counter (after a 2 clock period delay).