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silicon_labs_silabs_c8051f_familly [2013/01/08 19:00] 127.0.0.1 external edit |
silicon_labs_silabs_c8051f_familly [2015/01/25 08:54] ko4bb |
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| - | The way the 8051 addresses various areas of memory using different types of calls is strange, and probably not very efficient, but it has served the 8051 architecture well, and if you use a C compiler (there are many very excellent C compilers for the 8051, including a free one), that is largely transparent (see below) | + | The way the 8051 addresses various areas of memory using different types of calls is strange, and probably not very efficient, but it has served the 8051 architecture well, and if you use a C compiler (there are several C compilers for the 8051, including a free one), that is largely transparent (see below) |
| When I went from the Motorola 6805 programmed in assembly to the 8051 (assembly also), what a headache, but as soon as I started using C on the 8051, what a pleasure. There was no going back. | When I went from the Motorola 6805 programmed in assembly to the 8051 (assembly also), what a headache, but as soon as I started using C on the 8051, what a pleasure. There was no going back. | ||
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| All their chips have a precision internal oscillator so that you can run the UART and other serial peripherals without a crystal, but a crystal is supported if you need it. The fast chips have a PLL so that you can run the chip very fast with a lower frequency crystal (cheaper and lower EMI). | All their chips have a precision internal oscillator so that you can run the UART and other serial peripherals without a crystal, but a crystal is supported if you need it. The fast chips have a PLL so that you can run the chip very fast with a lower frequency crystal (cheaper and lower EMI). | ||
| - | Their development system is USB/JTAG based and very effective, with source level debugging in C, single stepping and all the debug facilities you would expect from a top of the line system. For the low-pin-count chips, Silabs has a 2 pin variant of the JTAG (they call it C2) which provides all the same debugging capabilities using only two pins, and these pins can even be used for normal I/O once you are done debugging. All this is completely transparent. | + | Their development system is USB/JTAG based and very effective, with source level debugging in C, single stepping and all the debug facilities you would expect from a top of the line system. For the low-pin-count chips, Silabs has a 2 pin variant of the JTAG (they call it C2) which provides all the same debugging capabilities using only two pins, one is the Reset pin and the other can even be used for normal I/O once you are done debugging. All this is completely transparent. |
| I have two favorites in that family, the C8051F133 (or 123), which is close to the top of the line, with a 64 pin package, 100 MIPS and lots of flash, RAM and on-chip peripherals, and the C8051F530, which is an 18 pin SOIC with 8k of flash and a 12 bit A/D converter (and a UART, and a voltage reference, and a built-in voltage regulator, and ...) Being a standard half-pitch SOIC, it can be soldered by hand without difficulty. | I have two favorites in that family, the C8051F133 (or 123), which is close to the top of the line, with a 64 pin package, 100 MIPS and lots of flash, RAM and on-chip peripherals, and the C8051F530, which is an 18 pin SOIC with 8k of flash and a 12 bit A/D converter (and a UART, and a voltage reference, and a built-in voltage regulator, and ...) Being a standard half-pitch SOIC, it can be soldered by hand without difficulty. | ||