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Often one may need to measure the time delay between 2 signals or the duration of a pulse with high resolution. One can either use a counter with a very high frequency clock or one can use an interpolator circuit to interpolate between clock cycles with high resolution.
A narrow range time to digital converter (TDC) can be used to measure the input to output delay of a synchroniser which typically varies for each input transition over a range of 1 clock period. The delay can be as low as 1 to 2 clock periods or 2-3 clock periods or more dependent on the synchroniser design.
The resolution of such time to digital converters are equivalent to that possible when using a counter and synchroniser clocked at very high frequency. Typically the resolution is equivalent to that obtained with a clock frequency of 10GHz or higher. State of the art TDCs have a resolution equivalent to that obtained with a clock frequency of 1 THz or more.
A capacitor is charged by a fixed current for the time interval to be measured. An ADC is used to measure the capacitor voltage after it stops charging. Between measurements the capacitor voltage is reset to zero. A resolution of 100ps is readily achieved when measuring time intervals of 400ns or less using a 12 bit ADC. State of the art TACs achieve a resolution of around 1ps
Dual slope/ramp TDC
A capacitor is charged by a fixed low noise runup current for the time interval to be measured. The time to discharge the capacitor to zero with a small current (perhaps 1/100 to 1/1000 of the charging current) is measured. Between measurements the capacitor voltage is reset to zero. A state of the art dual ramp TDC can achieve a resolution of 1ps or better with a 100ns range. With appropriate the design ( see ZCD design) the output zero crossing jitter is so low that a TAC with 100ps resolution may be required to achieve 1ps resolution at the dual ramp TDC input.
A capacitor is charged by a fixed low noise runup current for the time interval to be measured. The capacitor voltage is then rundown by a low noise current equal in magnitude to the runup current source. The zero crossing detector synchroniser will cause capacitor charge will overshoot zero but the time for which the capacitor is discharged is accurately known. The capacitor voltage is then runup through zero using a current of say 1/4 the original current and again the runup time is measured. This cycle is repeated each time using a current source of the appropriate polarity but 1/4 the magnitude of the current used in the previous cycle. After 10 cycles the runup time can be determined by the weighted sum of the various runup and rundown times to within 1ppm of the TDC's full scale range. The rundown sequence is similar to that employed by the HP3458A DVM ( HP3458A) For the final cycles the output zero crossing slope is so small that a Collin's style ZCD is required. The total rundown time of such a multislope TDC is much shorter than that required by a dual slope TDC of the same resolution. At the end of the rundown sequence the capacitor voltage is reset to zero by a shunt switch. This switch remains on between measurements.
A capacitor is charged by a fixed low noise runup current for the time interval to be measured. The capacitor voltage is then rundown by a low noise current of perhaps 1/4 to 1/8 of the magnitude to the runup current source. The zero crossing detector synchroniser will cause capacitor charge will overshoot zero but the time for which the capacitor is discharged is accurately known. The residual capacitor voltage is amplified and sampled by an ADC. To avoid amplifier saturation the amplifier gain is held at 1 until the current source discharge cycle is completed. This technique extends the effective resolution by 4 to 6 bits beyond that of the ADC. Thus a 12 bit ADC can be used to achieve 16-18 bit time interval resolution. Total conversion time is much shorter than that of an equivalent dual slope TDC. At the completion of the ADC conversion the capacitor voltage is reset to zero by a shunt switch. This switch remains on between measurements.
A tapped delay line with one flipflop connected to each tap. Either the flipflop data input can be connected to the tap with all flipflops driven by the same clock, or the flipflop clock can be connected to the tap with all data inputs driven by the same signal. The resultant thermometer code produced by the flipflop array outputs then be decoded to determine at which tap the flipflop data and clock transitions were coincident. The tapped delay line can consist of a string of gates or to provide finer resolution, a vernier tapped delay line technique is used. In the vernier tapped delay line technique one tapped delay line drives the flipflop clock inputs, whilst another tapped delay line drives the flipflop data inputs. The clock tap delay is slightly longer (or shorter) than the data tap delay. The effective tap delay is then the difference between the clock and data tap delays.
Either the effective tap delay is measured or either a DLL or PLL is used to regulate the tap delay by adjusting the tapped gate delay chain supply voltage.
A large number of arbiters are driven by the input signal and a clock. Since the delay of all arbiters are not identical due to process statistical variations they will not all make the same decision. The number of arbiters whose outputs are logical 1 after the signal transition follows a cumulative Gaussian distribution as the time delay between the signal transition and the clock is varied. Thus by counting the number of arbiters that are logical 1 after the signal transition the signal to clock delay can be determined. The effective range is very narrow and process dependent, calibration is required.
Subpicosecond resolution is possible. Statistical TDCs are useful for measuring timing jitter, and in PLLs.
The input signal transition is converted to a quasi gaussian pulse by low pass filtering the output of a short pulse triggered by the input signal transition. The resultant pulse is then sampled by a pipeline ADC clocked by a low jitter high frequency (100MHz) clock. The position of the centroid of the pulse is then calculated from the ADC output samples. A resolution of around 10ps or better is possible when using a 16 bit pipeline ADC clocked at 80MHz or so.
The input signal is low pass filtered and then sampled by a pipeline ADC clocked by a low jitter high frequency (100MHz) clock. The position of the midpoint of the low pass filtered input signal transition is then calculated from the ADC samples. A resolution of around 10ps or so is possible when using a 16 bit pipeline ADC clocked at 80MHz or more.
A pair of inphase (sine) and quadrature phase (cosine) samples of a sinewave are taken at the input signal transition. Usually a pair of ADCs simultaneously sample a pair of inphase and quadrature sinewaves but other implementations are possible. A dual phase synchroniser is used to synchronously take 2 samples of a continously clocked counter. The counter is clocked by a shaped version of the inphase sinewave. The dual phase synchroniser consists of two synchronisers, the input flipflop of one synchroniser is clocked by a shaped version of the inphase sinewave whilst the input flipflop of the other synchroniser is clocked by a shaped version of the quadrature phase sinewave.
One of the synchronisers of the 2 phase synchroniser will sample the count at the next but 1 counter clock transition after the input signal, transition whilst the other may sample the counter at this clock edge or it may sample the counter one clock period later. The sine and cosine samples are used to calculate the delay from the inphase sinewave positive slope zero crossing to the input signal transition. This result is then used to select the count sample for which the synchroniser input stage setup and hold time constraints were met so that the count sample can be relied upon to have occurred at the next but counter clock active edge after the input signal transition.
A resolution of a few tens of picosec or so is possible when sampling 10MHz inphase and quadrature sinewaves with 14 bit ADCs like the LTC1407A-1. It is also possible to measure the distortion and quadrature error of the complete system (ADC and sinewave reference signals) so that correction for these errors is possible.
In a variation of this technique a sequence of sine and cosine samples are simultaneously taken of progressively lower frequency sinewaves. The highest frequency sinewaves determine the resolution whilst the lower frequency sinewave sine and cosine samples are used to resolve cycle ambiguities.
This technique starts a triggered vernier oscillator at the input signal transition and measures the time number of vernier clock cycles from the input signal transition that triggers thevernier oscillator until coincidence to occurs between the transitions of the vernier oscillator and a low noise reference clock. If the vernier oscillator frequency differs from that of the reference clock by 1% the resolution is about 1/100 of the clock period. The difficulties associated with drift in the triggered vernier oscillator were solved by the invention of the triggered phase locked vernier oscillator technique used in the HP5370A/B time interval counters. The 5370A/B time interval counters have a resolution of 20ps.
The input signal triggers a damped sine generator, the output of which is buffered and sampled by an RF sampling ADC. The time corresponding to an input transition can be determined by fitting a damped sine to the ADC samples. Picosecond resolution (5ps or better) and noise is achievable.
The input signal drives an impulse generator which in turn drives a bandpass filter (e,g. SAW bandpass filter) the output of which is amplified to drive an RF sampling ADC (e.g. pipeline ADC). The location of the cross correlation peak of the output signals due to successive impulses is used to infer the time interval between the corresponding input signal transitions. Resolution and noise can be as low as a few tens of femtosec.
The input signal drives an electrooptical modulator whose output is stretched and converted back to an electrical signal which is sampled by an RF sampling ADC. An effective sampling rate of 100GHz or more can be achieved allowing femtosecond resolution.
NOTES
The maximum input output delay of the synchroniser determines the required range of a TDC when it is being used as an interpolator. If a slightly more complex dual phase synchroniser design is used then the input signal transition can sample the state of a clock in phase quadrature with the synchroniser clock. The output of this flipflop once settled is used to select the output of the synchroniser, that has settled with high probability, as the input to the final flipflop, the output of which is used to sample the counter. This reduces the number of count sample registers usually required when using a dual phase synchroniser from 1 to 2 and the interpolator output is not required to allow post facto selection of the correct count sample. The maximum synchroniser delay is also reduced so a higher resolution TDC with a shorter range can be used. The exact phase shift of the quadrature phase clock with respect to the reference clock isn't too critical as the state of this clock as sampled by the input transition to select the output of the synchroniser whose input flipflop meets its timing margins when it samples the input signal.
TBC...
REFERENCES
1) Simulation of picosecond detector electronics approaches
5) ACAM GP2 Tapped delay line TDC
6) 3 stage stabilised delay line interpolator
8) A HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTER AND CALIBRATION SCHEME
9) Zeus Timing system performance
11) Femtosecond resolution on chip timing measurement
12) HP Journal issue with article on HP5370A time interval counter
13) Implementation of a high resolution TDC in an FPGA
14) Accurate Time Interval Measurement Electronics.
15) Review of subnanosecond time interval measurements
16) Review of methods for time interval measurements with picosecond resolution