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Phase Detectors For PLL Applications

—–Original Message—–

From: microwave-bounces@echo.valinet.com

On Behalf Of Loren Moline WA7SKT


A while back I asked a question about phase detectectors.

Now my question is this. The Macom and other brick PLO's use a different type of phase/frequency detector. Somehow the phase noise is very low on these. All I know is when I listen to a carrier at the IF of my downconverter using one of these PLO's it is a very nice sounding note with no apparent distortion.

Because these PLO bricks do not have a frequency divider it would seem that one could use the same kind of detector to lock our own oscillators.

Has anyone seen a project in which you can build or buy this kind of phase/frequency detector and lock an oscillator every 10 MHz using this standard like the Macom bricks do? And the support loop filter necessary to support such a lock? Thanks!


Thomas, Nx1N answers:

There are two common types of phase detectors. One uses a digital divider to divide the VCO down by some ratio. (This is the basis of DDS systems, BTW.) For example, an 8 GHz VCO divided by 80 gives 100 MHz output. This is applied in to a mixer and a 100 MHz LO. The output of the mixer is filtered, represents phase, and is used to lock the 8 GHz VCO.

There is jitter in the digital division process (going through 7 flip-flops, in this case), and that jitter adds to the normal log(xN??) phase noise of any common multiplier scheme.

The other basic type is a sampling PLL and does not use a mixer. A step recovery diode (SRD) is driven by a 17 dBm to 20 dBm signal at 100 MHz. When the current in the diode shuts off during the negative half-cycle, it creates a voltage spike of perhaps 60 picosecnds in width. That spike is used in a (typically) 2-diode “sampling bridge” arrangement to act as a simple rilly-fast SPDT switch.

Effectively, one end of that SPDT switch is connected to the 8 GHz VCO and the other end to a small capacitor. Because the switch is closed cyclically at a 100 MHz rate (for the above example), it may happen to sample the 8 GHz at the same relative point on its sinusoid. If that is the case, the VCO is in lock with the 100 MHz reference. The “DC” on the capacitor is filtered and used to lock the 8 GHz VCO as for the digital case.

Which form is better? Both methods incur phase noise proportional to the multiplication factor (80x, in this case), based on the log of the ratio. However, the digital divider case adds an additional phase noise contribution from jitter in the divider flip-flops. The actual voltage switching point of each flop's clock input signal is fairly precise, but 'fairly' doesn't cut it, so it adds jitter. You generally will hear less phase noise on the sampled-VCO case, the most common brick lock method.

Thomas, Nx1N

Thomas A. Visel, CTO Neuric Technologies, LLC “We've put some real thought into Artificial Intelligence!”

Didier KO4BB adds:

Actually there is a third type of phase detector, closely related to the Step Recovery Diode Sampling Phase Detector, it is the old fashioned mixer. Like the SRD Sampling Detector, is it an analog phase detector, but it is not as effective when used to sample a high order harmonic of the reference frequency.

The main limitation (or advantage, as shown below) of the sampling phase detector is that there is uncertainty on the harmonic of the signal being sampled, so these detectors are mostly practical when you are trying to phase lock a fixed frequency oscillator, such as a brick oscillator. It is hard to use that method to phase lock a multi-octave VCO (such as a YIG oscillator) for instance. It's been done, such as in the Tektronix 494 Spectrum Analyzer, with significant complexity but excellent phase noise performance compared to a digital synthesizer.

Here is a simple schematic of a sampling phase detector suitable for 0 Hz IF output. SRD is a Step Recovery Diode, D2 and D3 are Schottky detectors:

There are several application notes on Sampling Detectors in my Manuals page


Didier KO4BB

Bill, N6GHZ adds:

Hi Tom,

You described the sampling phase detector very well along with its advantages. Best description I'll heard in awhile.

I would only add that the sampling phase detector was adopted by California Microwave, Frequency West and all the rest since then, after it was well described by Textronix as the key component in their sampling oscilloscopes, introduced commercially in the late 50's, early sixties. The other key ingredient was the invention and commercialization of the SRD by HP a little later (mid 60's).

One other significant advantage of the impulse generator/sampling phase detector combo is the ability to operate at ALL multiples of the impulse frequency (at least up to about 20 to 30% of the width of the impulse). This allows odd multiples like 7, 11, 13, 15 and all the rest. In the 60's through 70's not many digital dividers (actually none that I ever knew of) could be made to duplicate that function.

The other key design feature of the CMI/Frequency West PLO's is the cavity oscillator at L band. If you look at the phase noise of the high Q cavity oscillator by itself, many will be surprised by its outstanding short term stability and low phase noise.

That neat combination of PLL signal source technology is only out done in overall phase noise performance by the double cavity klystron, and we know that device isn't to handy to use in the shack.

I think that will explain, Loren, why using the cavity PLO, like the “brick”, yields a very nice sounding note from your converter.

Regards…Bill - N6GHZ

John, KE5FX adds:

All very true, but don't underestimate what can be done with modern off-the-shelf digital parts. Using a low N-factor in your loop is THE most important factor in PN performance regardless of the technology used. Bricks with N=80-100 have that advantage right out of the starting gate.

A clean VCO is also very important as Bill points out. If the VCO is dirty enough, it will degrade the inband PLL noise substantially. The loop filter is not a brick wall, even though many PLL texts tend to treat it that way.

There's an interesting phase-noise plot near the bottom of the page I posted recently at http://www.thegleam.com/ke5fx/hpll.htm , specifically the light-blue trace (Frequency West brick) and magenta trace (homebrew PLL). This is an 8-GHz PLL built with off-the-shelf components and configured with DIP switches for an 'N' factor of 80, suitable for direct comparison with the brick.

The PLL is as quiet as the brick at offsets below 1 kHz. (The brick appears slightly cleaner, but the difference is small, and within the margin of error for this type of measurement.) Then the brick pulls ahead in the horse race. It is 10 dB quieter by 10 kHz, and 30 dB quieter at 100 kHz.

Because the close-in noise is comparable, it can be concluded that the cheap monolithic VCO – and NOT the choice of a particular phase-detector topology or the use of digital dividers instead of an SRD multiplier – is responsible for most of the impairment.

Ultimately it's kind of pointless to build something like this, given that bricks are $50 on a bad day. But you don't really remember where the bodies are buried unless you hold the shovel yourself.

– john, KE5FX

The last word by Skyworks (http://www.skyworksinc.com):

Theory And Application Of A Sampling Phase Detector 1/18/2006

By Skyworks Solutions, Inc.

The phase lock of a Voltage Controlled Oscillator for VHF, UHF and microwave frequencies is very important in communications and radar application. It combines the far-out phase noise of fundamental oscillators, especially in the microwave frequency range (100 kHz away from carrier frequency and beyond), the excellent long-term stability, and the close-in phase noise of a crystal oscillator (from carrier frequency to 100 kHz away).

A voltage-controlled oscillator can be phase locked by two methods:

  1. Digital phase lock: This is usually achieved by using a frequency divider to divide the higher frequency of the VCO to the same frequency of the crystal reference. A digital phase detector is then used to acquire the phase lock. The advantage of this method is that it is self-acquiring and can operate at very low frequencies. It is widely used at low frequencies from 1 MHz up to 3 GHz. However, this method also has two disadvantages. First, the noise floor of the divider will limit its phase noise; and second, at microwave frequencies it will not be economical.
  2. Analog phase lock: This is achieved by using an SRD as a comb generator to create a comb of reference frequencies to the frequency of the VCO. The phase detecting is accomplished by using a mixer to detect the phase differences between the reference and the VCO. The Skyworks sampling phase detector is designed to perform the analog phase lock in a simple and more economical way.

The sampling phase detector used in phase lock of a VCO operating by the theory of principles of feedback control systems.

The error signal output of the sampling phase detector Vbeat = Em sin is the differential phase error between the VCO and the crystal oscillator. The loop amplifier amplifies the error signal to the VCO and corrects the VCO to be in phase with the crystal oscillator. At the same time, the loop amplifier acts as a low pass filter and filters away the crystal frequency.

This method of phase lock will achieve the lowest phase noise possible beside the theoretical degradation of 20 log N, where N is the multiplication factor between the crystal oscillator and the VCO. The other circuits that will generate additional noise are the driver amplifier, sampling phase detector, and the loop amplifier. They may all contribute to further degradation in phase noise (typically 1 dB if the crystal oscillator has a noise floor of -155 dBc/Hz or 3 dB if the crystal oscillator noise floor is -160 dBc/Hz).

ham_radio/phase_detectors_for_pll_applications.txt · Last modified: 2013/01/10 19:00 (external edit)
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