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Dual Mixer systems


Offset Sources

Sometimes it is possible to tune a low phase noise high stability OCXO to the desired offset frequency. A frequency synthesizer can sometimes be used however it may have lowest noise and spurs at some weird offset frequency like 13.3333 Hz which may not be convenient. The highest performance usually requires a custom synthesiser employing a cascaded pair of lower sideband and upper sideband mixers combined with a a pair of low noise dividers and a low phase noise crystal oscillator phase locked to the synthesiser output to eliminate unwanted spurs.


Mixer Port Terminations

To minimise the mixer noise contributions the mixer IF port should be terminated with a capacitor and the dc load resistance should be high. Both the RF and LO ports should be saturated.

To minimise mixer phase shift tempco the RF and LO ports should include series resistors to reduce their VSWR.

The Mixer IF port beat frequency waveform will be approximately trapezoidal when the mixer is driven and terminated as recommended. The slew rate at the beat frequency waveform zero crossings will be significantly greater than that with a sinusoidal beat frequency waveform of the same amplitude.

Mixer phase shift tempco

With 10MHz mixer input frequencies the equivalent phase shift tempco of a diode DBM can be as high as 10-20ps/C. This can be reduced significantly by minimising the mixer input port(RF and IF) VSWR. Even so the temperatures of the 2 mixers used in a DMTD should track to better than around 1mK or so to avoid degrading system performance. Using a higher mixer input frequency (100MHz) can reduce the mixer phase shift tempco to 2ps/C or less.



Zero Crossing Detectors (ZCD)

The low frequency trapezoidal beat frequency waveform has too low a slew rate to drive a time interval counter without excessive jitter. A slope amplifier (zero crossing detector) is required to amplify the zero crossing slope to produce an output with a slew rate of 1V/us or greater to minimise the jitter added by the time interval counter input circuitry.

A seminal paper on optimal zero crossing detector design was published by Oliver Collins in 1996 (“The Design of Low Jitter Hard Limiters” IEEE transactions on Communications, Vol 44 No 5, May 1996 pp 601-608) Collins shows how to account for the effect of clamping diodes on the output noise of a limiter/filter stage. He shows that the optimum limiter consists of a relatively large number of cascaded limiter/filter stages with the gain of and bandwidth of each successive stage larger than its predecessors. In practice a ZCD consisting of as few as 6 cascaded stages or even less may have a performance not significantly worse than the theoretical optimum.

The file ( http://www.ko4bb.com/wiki/Bruce/GeneralisedCollinsHardLimiterPaper.pdf ) extends the Collins analysis to include the common case where the the equivalent input noise of each limiter/filter stage are all different.

The following set of guidelines are useful for calculating the equivalent input noise for non inverting and inverting filter/limiter stages.

Non inverting limiter/filter stages

In the above circuit the dc gain is (1 + R102/R101).

When calculating the jitter contribution of this stage the effective input noise includes:

        o The amplifier input noise voltage
        o The noise voltage produced by the amplifier input noise current flowing through R101||R102
        o The noise voltage produced by the input noise current of the next stage flowing through R103 divided by the dc gain.
        o The Johnson noise of R101||R102
        o The Johnson noise of R103 divided by the dc gain
        o For the first stage the mixer output noise contributes to the effective input noise of the first stage.

High gain stages

Sometimes the gain of the stage is too high to avoid amplifier saturation when using the above noninverting amplifier configuration. In this case additional clamp diodes across a portion of the feedback resistor may be required to avoid amplifier saturation as shown below.

In the above circuit the dc gain is (1 + (R103 +R102/R101) ) and the gain when either of the auxiliary diodes (D101, D102) is conducting (1+ R102/R101) is chosen to be larger than the minimum stable gain of U101. This can allow a decompensated opamp (eg. OP37) with a high gain bandwidth product but which isnt unity gain stable to be used.


Inverting limiter/filter stages

In the above circuit the dc gain is -(R102/R101) When calculating the jitter contribution of this stage the effective input noise includes:

        o The opamp input noise voltage
        o The noise voltage produced by the opamp input noise current flowing through R101||R102
        o The Johnson noise of R101||R102
        o The opamp input noise voltage of any preceding such inverting amplifier limiter stage.
        o The opamp input noise voltage of this inverting stage contributes to the effective input noise of the following stage.
        o For the first stage the mixer output noise contributes to the effective input noise of the first stage.

High gain wide bandwidth stages

Sometimes, particularly for the last high gain wide bandwidth stage of the filter limiter cascade, it is difficult to achieve the required gain and bandwidth using a single opamp, especially if the phase shift contribution of the opamp is to be kept small so that the phase shift and delay is dominated by the passive filter components. In this case either a wideband opamp like an AD829 with external compensation can be useful. Sometimes even the AD829 has inadequate gain bandwidth so that a cascaded pair of opamps as illustrated below may be required. A current feedback opamp like an AD811 can often be used as the second opamp without major effect on the effective input flicker noise of this stage.


ZCD Phase shift tempco

The phase shift tempco of a ZCD is dominated by the tempco of the low pass filter components used in the fist stage output low pass filter. A high performance 5 stage Collins style ZCD design with a 10Hz input beat frequency may have a first stage output RC filter time constant of around 2 millisec. Even when a resistor with a tempco of 15ppm/C or less are used together with NPO/C0G capacitor the phase shift tempco for a 10MHz mixer input frequency may be as high as 10-20fs/C. Subsequent stages have equivalent output filter phase shift tempcos less than 1/2 this. Consequently the temperature of the pair of ZCD's used in a DMTD system should track to better than 1C to avoid degrading the system performance.

ZCD Design Example

Given a mixer with a 10Hz 0.7V pp trapezoidal beat frequency output with a zero crossing slew rate of 50V/s. A ZCD slope gain of 100,000 is required to achieve a 5V/us ZCD output slew rate. If the input noise is 10nV/rtHz for all ZCD stages and a 6 stage ZCD is used then the optimum filter time constants and dc gains for each stage are:


Testing ZCD performance

When evaluating ZCD performance a trapezoidal waveform generator with low output jitter can be used to drive a a pair of ZCD's in parallel. The time delay jitter between the 2 ZCD outputs is then measured. If the ZCDs are assumed identical then the jitter of a single ZCD is 0.7*measured jitter. However since ZCDs are used in pairs in a DMTD system this calculation may not be necessary. The trapezoidal waveform generator can be used to drive 3 ZCDs in parallel so that a 3 cornered hat technique can be employed to determine the jitter characteristics of each individual ZCD. To evaluate ZCDs with subnanosecond jitter with a 10Hz input frequency, the trapezoidal generator should have a jitter of 25ps/rtHz or less. Such trapezoidal waveform generators are not off the shelf items.

The simplest trapezoidal generator with sufficiently low jitter uses a low jitter digital divider to divide down a low phase noise crystal oscillator output to the required frequency. The divider output is then used to ramp an integrator with low noise feedback clamps up and down. A resistive divider at the integrator output is then used to attenuate the signal to the required level and set the generator output impedance.

The above trapezoidal waveform generator has a jitter of around 100ps/rtHz, which is adequate for simulating the noisier mixers. However a jitter about 5x lower than this is required to simulate the quieter mixers. To achieve this either each of the LM329's can be replaced by 25 LM329's whose voltages are averaged by a resistor network for a total of 100 LM329's or a quieter reference voltage source is required. Since the noise of a forward biased diode (including LEDs) is much lower than the noise of a diode in avalanche breakdown (even a buried zener like an LM329), a reference consisting of series stack of forward biased LEDs can be much quieter than an LM329. A ZCD trapezoidal waveform test generator employing series connected LEDs as references is shown below.

In the above circuit the input transition to corresponding output zero crossing delay is nominally temperature compensated if identical LEDs and diodes are used both in the current sources and in the integrator feedback clamp circuit. However the waveform amplitude will be temperature dependent with a negative tempco, this isnt particularly significant as the mixer beat frequency output waveform is also temperature dependent albeit with a positive tempco.



Cable phase shift tempcos

The time delay tempco of an RF cable and depends on the cable dielectric and construction. It can be as high as 0.5ps/C/m for some cables. Thus the lengths of RF cables used should be kept short and wherever possible cables connecting the sources to the mixer inputs should have the same length, and have the same temperature. Since a well designed DMTD system has a resolution of 0.01ps or less at the mixer RF input frequency, ensuring that cable delay tempcos match is critical to achieving such performance.



Isolation Amplifiers


A 10MHz isolation amplifier having a reverse isolation of 120dB has a worst case phase shift variation due to load VSWR variations of 100fs. To ensure that phase shift due to cross talk and load VSWR is 10fS or less the reverse isolation and cross talk need to be greater than 140dB. A significant reduction in phase shift due to load VSWR is achieved if the the lenght of the cable connected the isolation amplifier to the load is close to an odd multiple of one-half the signal wavelength (½l) in the cable.

Amplifier phase shift tempco

The phase shift tempco of a state of the art 10MHz isolation amplifier can be as low as 1ps/C. Using a bandpass filter with a Q of 10 will degrade this to 30ps/C or worse depending on the filter component tempcos. Achieving a system stability of 10fs or better requires stabilising the isolation amplifier temperature to better than 10mK when no bandpass filter is used. When a bandpass filter is used the temperature of the bandpass filter would need to be stabilised to better than 300uK to maintain the same performance. Whilst stabilising the isolation amplifier temperature to 10mK or so is challenging it can be done. Stabilising a bandpass filter temperature to better than 300uK is very expensive and very difficult to achieve.



Picket fence technique


Thermal enclosure (oven) design:


precision_timing/dual_mixer_time_difference_systems.txt · Last modified: 2013/02/05 19:00 (external edit)
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